關於 engineering verification test ，我們在網路上蒐集到這些相關的討論、資訊與評價

［ASML Recruiting］ IC Design Engineer

The job is located in Hsinchu/Tainan that could work on the advanced analog and mixed signal ASIC for next generation electron detection channel for the leading edge e-beam inspection and metrology systems with work life balance.

The following are the Job Descriptions for this opportunity
• Develop the functional blocks of high-speed Analog-to-Digital Converter (ADC) and/or Phase-Locked Loop (PLL) in ASIC for the detection channel of electron beam inspection tools, including:
• Define the design specifications of the Read-Out Integrated Chip (ROIC) or chipset based on product roadmap and System Performance Specifications (SPS) defined by system engineer.
• Develop new circuit architecture and technical solutions for next generation ASICs in detection channel, including feasibility study, schematic design, pre-layout simulation, layout design, and post-layout simulation.
• Cooperate with Printed Circuit Board (PCB) designer to design Evaluation Board (EVB) and with test engineer to test and characterize the ASICs.
• Create Element Design Specifications (EDS) and Test Performance Specifications (TPS) based on detail ASIC design and chip test/verification.
• Cooperate with IC design partner to develop the ASICs for detection channel of of electron beam inspection tools, including:
• Review the detail schematic and layout design, TPS, and test results from our partner during the ASIC industrialization phase.
• Together with the engineering team from the partners, identify design solutions to achieve the specifications of the module/function. Review the design details and simulation results from our partner.
• Support module level and sub-system level integration
• Generate and / or review related IP documents

Provide with more information about the position: D&E - IC Design Engineer - Tainan/Hsinchu - Jobs | ASML
https://www.asml.com/en/careers/find-your-job/2/4/9/de-ic-design-engineer-tainanhsinchu-req24973

Talk Announcement-9/18 Friday 10am, Prof. Shawn Blanton from CMU

Date/Time：2015/09/18(Fri) AM10:00-12:00
Venue： Engineering Bldg. 4, ED 528
Speaker： Prof. Shawn Blanton
Dept. of Electrical and Computer Engineering, Carnegie Mellon University
Topic: Improving Design, Manufacturing, and Even Test through Test-Data Mining
Abstract: Since yield is not 100%, the main objective of manufacturing test has and continues to be screening out “bad” ICs. Today, however, test is being used to provide valuable information about failing chips, answering questions about whether the design, the fabrication process or some combination of the two is responsible for failure. The information extracted is, ideally, used to improve design, fabrication and even test itself. In this talk, an overview of research in the Carnegie Mellon Advanced Chip Testing Laboratory (http://www.ece.cmu.edu/~actl) in this area will be described. Experiment results from manufactured chips from both integrated device manufacturers (e.g., IBM) and chip-design houses (e.g., Nvidia) will be used to illustrate the utility of the described approaches.
Speaker's brief bio: Shawn Blanton is a professor in the Department of Electrical and Computer Engineering at Carnegie Mellon University where he formerly served as director of the Center for Silicon System Implementation, an organization that consisted of 18 faculty members and over 80 students that focused on the design and manufacture of silicon-based systems. He currently serves as the Associate Director of the SYSU-CMU Joint Institute of Engineering (JIE, http://jie.cmu.edu/). He received the Bachelor's degree in engineering from Calvin College in 1987, a Master's degree in Electrical Engineering in 1989 from the University of Arizona, and a Ph.D. degree in Computer Science and Engineering from the University of Michigan, Ann Arbor in 1995.

Professor Blanton’s research interests are housed in the Advanced Chip Testing Laboratory (ACTL, www.ece.cmu.edu/~actl) and include the design, verification, test and diagnosis of integrated, heterogeneous systems. He has published many papers in these areas and has several issued and pending patents in the area of IC test and diagnosis. Prof. Blanton has received the National Science Foundation Career Award for the development of a microelectromechanical systems (MEMS) testing methodology and two IBM Faculty Partnership Awards. He is a Fellow of the IEEE, and is the recipient of the 2006 Emerald Award for outstanding leadership in recruiting and mentoring minorities for advanced degrees in science and technology.

Your attendance is most welcome!


Aileen Yu 游雅玲
EECS International Graduate Program
National Chiao Tung University
http://eecsigp.nctu.edu.tw/
Tel:+886-3-5131290, +886-3-5712121 ext:54019
Email:[email protected]